1. Field of the Invention
The present invention relates to a voltage controlled oscillator formed of a semiconductor integrated circuit having an advantage of high-speed oscillation.
2. Description of Related Art
In recent years, voltage controlled oscillators have been used in general equipment containing PLL (Phase Locked Loop) circuits, for example, used for an oscillator frequency control in automatic frequency control device, a satellite tracking receiver in signal tracking device, a frequency modulated signal demodulation device (FM receiver), a carrier regeneration control, a pulse synchronization control and a timing extraction in narrow band selecting device, multiplication frequency generation in industrial/consumer electronic equipment, and especially, a frequency synthesizer in mobile communication equipment, then the demand for them is further growing.
FIG. 10 is a circuit diagram showing a differential circuit used in a conventional voltage controlled oscillator, and FIG. 11 is an equivalent circuit diagram showing the same conventional differential circuit. In these figures, reference numeral 1 denotes a differential circuit, reference signs M1 and M2 denote PMOS transistors and reference signs M3, M4 and M5 denote NMOS transistors.
The differential circuit 1 in FIG. 10 is used for a VCO (voltage controlled oscillator) in which to achieve a high-speed oscillation frequency is required, and it is disclosed by Ian A. Young et al. (xe2x80x9cA PLL Clock Generator with five to ten 100 MHz of Lock Range for Microprocessorsxe2x80x9d IEEE JSSC, Vol. 27, No. 11, November 1992). To sources of the transistors M1 and M2 a voltage of power supply Vcc is supplied and a bias voltage Vp is applied to gates of the transistors M1 and M2. A drain of the transistor M1 is connected to a drain of the transistor M3, and a differential output Vo+ is output from this connection point. Further, a drain of the transistor M2 is connected to a drain of the transistor M4, and a differential output Voxe2x88x92 is output from this connection point. A differential input Vi+ is input to a gate of the transistor M3 and a differential input Vixe2x88x92 is input to a gate of the transistor M4. Sources of the transistors M3 and M4 are connected to a drain of the transistor M5, a bias voltage Vn is applied to a gate of the transistor M5 and a source thereof is connected to a ground GND.
A voltage controlled oscillator consists of a plurality of differential circuits 1 which are concatenated in a ring shape and includes a voltage control unit 2 for controlling the bias voltages Vp and Vn which are applied to these differential circuits 1. One example of the voltage controlled oscillator (ring oscillator) consisting of the differential circuits 1 is shown in the equivalent circuit diagram of FIG. 12.
Next, an operation will be discussed.
The bias voltage Vp are so applied to the transistors M1 and M2 that the transistors M1 and M2 operate in a linear region to be used as resistor Rp, and the bias voltage Vn is so applied to the transistor M5 that the transistor M5 operates in a saturation region to be used as a current source. At this time, in the differential circuit 1, parasitic capacitance Cm are present at output points on the drain sides of the transistors M1 and M2 (apparently as viewed from the side of the circuit outputs). In order for the differential circuit 1 to perform a stable oscillation, the bias voltages Vp and Vn should be so set that the oscillation amplitude Vosc always satisfies the following equation (1):
Vosc=Itailxc3x97Rpxe2x80x83xe2x80x83(1) 
(where Itail denotes a current value of the current source transistor M5)
A differential circuit performs a more stable operation than an inverter circuit even if the oscillation amplitude is small and therefore has the advantage of high speed and low jitter. If still higher speed is required, however, when the parasitic capacitance Cm which are apparently present as viewed from the side of the output points (outputs Vo+ and Voxe2x88x92) become larger, the parasitic capacitance Cm increases the transfer delay time as gate-drain feedback capacitance (mirror capacitance) to have an ill effect on the oscillation amplitude, thereby putting a limitation on an available oscillation frequency of this circuit.
The present invention is intended to solve the above described problem and it is an object of the present invention to provide a voltage controlled oscillator capable of responding to a speedup in oscillation frequency by suppressing the parasitic capacitance.
A voltage controlled oscillator according to one aspect of the present invention, it is characterized by that the resistance elements are formed of a plurality of transistors as a plurality of resistance elements connected in series to one another; and a resistance element among the resistance elements provided on a side of output point of the differential circuit are formed of transistors having a small transistor size.
A voltage controlled oscillator according to another aspect of the present invention, it is characterized by that the resistance elements include a first resistance element, a second resistance element and a third resistance element which are connected in series to one another and formed of respective transistors; the transistors forming the second and third resistance elements are biased into a linear region deeper than that of the transistor forming the first resistance element; and the third resistance element provided on the side of output point of the differential circuit is formed of transistors having a small transistor size.